Chapter 11

11–1 INTRO TO I/O INTERFACE

Hardware interfaces - connection and communication of different devices

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分类

根据信息流方向
- Input interface
- Output interface
根据信号类型
- Analog interface
- Digital interface
根据数据传输方式
- Serial interface
- Parallel interface

Structure of Hardware Interface

An I/O interface unit contains the following blocks:
- Read/Write Control Logic
- Data Bus Buffer
- Port register (e.g. port A, port B)
- Control and Status

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Key Points

如何连接 CPU 和 I/O 设备
- Latches for output interface
- Three state buffers for input interface
I/O 地址分配
I/O 地址译码
怎么同步 CPU 和 I/O 设备
- unconditional transfer for always-on devices
- strobing
- handshaking and polling
- interrupt-driven I/O
- channel-based I/O (e.g., DMA)

Isolated and Memory-Mapped I/O

Isolated I/O: uses the IN and OUT transfer data（PC）
- 优点 - 可以 fully use memory
- 缺点 - 只能用 IN/OUT 等指令 I/O，需要单独的控制信号，慢，编程复杂
Memory-mapped I/O: 访存指令传输
- 优点 - 快，编程简单
- 缺点 - limited I/O address space, slower response time

TTL & CMOS

两种 Logic ICs 硬件，有各自的 0/1 范围电压规定
CMOS 精度更高，只能 CMOS->TTL，不能反过来
老设备用 TTL（82C55
输入设备电路需要考虑
- TTL/CMOS compatible
- 减少/去除噪声
switch bounce (解决方法：滤波、double-throw 等等)

输出接口电路要求

部件和微处理器有 matching the voltage and current
Voltages are TTL-compatible
电流比 TTL 标准小

Basic Input and Output Interfaces

IN - I/O device to microprocessor
OUT - microprocessor to I/O
basic input device - 三态门的集合
basic output device - 锁存器的集合

Basic Input Interface

外部信号通过 buffer 连到处理器上
IN AL, 74H - 指令执行时，开关的数据存到 AL 寄存器中

Basic Output Interface

I/O 设备中常有 latch/filp-flops，暂时存储 CPU 输出的数据
\(\overline{SEL}\) - 当 CPU 启用它时，捕捉输出数据
OUT 38H, AL

Asynchronous Data Transfer

上面的情况中，CPU 和输入输出设备具有不同的时钟 - 异步
两种异步数据传输方法
- strobing (one control signal)
  - A strobe is a synchronization signal to indicate the start and end of a data transmission
  - source-initiated/destination-initiated transfer - stobe 由谁发出
  - 缺点：有效数据必须长时间保持，没有信号表明数据是否被成功接收，多级数据传输时，传输速度取决于最慢的部件
- handshaking (two control signal)
  - 两个信号，一个 request（from initiating unit），一个 reply
  - 注：先放上/撤销数据，再改变控制信号

Example - printer

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11–2 I/O PORT ADDRESS DECODING

Interfacing I/O device includes
- selection of I/O port
- transfer of data
I/O port address decoding
- memory-mapped I/O
- isolated I/O
  - less address pins
  - generates separate control signals

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one byte transfer - unaligned memory accesses

any 8-bit I/O write request requires separate write strobes
read 不需要

32 bit

11–3 THE PROGRAMMABLE PERIPHERAL

82C55

用于键盘 (60H–63H) 和打印机接口 (378H–37BH)

three I/O ports (labeled A, B, and C)
2 groups
- Group A (port A and the upper part of port C)
Basic Operation
通过两个内部 command registers 编程
- 如果 0 is placed in bit position 7 of byte A, byte B is selected

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Mode 0 Operation

Basic input/output operation

Mode 0 让 82C55：

可以作为输入buffer
可以作为输出latch

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The following example multiplexes the 8-digit display

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stepper motor - 把电信号转换成运动

Full-step Excitation Mode
- one-phase
- two-phase（力矩更稳定）
half-step
micro-step

Half-step Excitation Mode

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Micro-step Excitation Mode

Mode 1

Strobe input/output operation

the strobe, interrupt and other “hand shaking” signals are used
port C is used for control or handshaking signals

外部设备输入

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符号定义

\(\overline{STB}\) - strobe，把数据 load 到 port latch 里
\(IBF\) - Input buffer full，表明 input latch 包含了信息的一个输出
\(INTR\) - Interrupt request
\(INTB\) - Interrupt enable
\(\overline{signal}\) 意味着低电平有效

工作时序

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Example: keyboard

\(\overline{DAV}\) - 接 \(\overline{STB}\)

输出数据到外部设备

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符号定义

\(\overline{OBF}\) - Output buffer full，当 port A latch 有数据输出时有效，接收到 \(\overline{ACK}\) pulse 时，return 无效
\(\overline{ACK}\) - acknowledge signal

工作时序

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Example: 打印机

Mode 2 Bidirectional Operation

既要输入又要输出

group A only

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11–4 8254 PROGRAMMABLE INTERVAL TIMER

三个可编程 counters (timers)

Timer 0 generates an 18.2 Hz signal that interrupts the microprocessor for a clock tick.
- often used to time programs and events in DOS
Timer 1 is programmed for 15 µs, used on the PC to request a DMA action used to refresh the dynamic RAM.
Timer 2 is programmed to generate a tone on the PC speaker.
Each timer contains
- CLK input
- gate input
- output

Modes of Operation - 6 种编程模式

Mode 0: interrupt at the end of count
- 计数归零时 OUT = 1
- Gate 低电平时 disable
Mode 1: hardware retriggerable one-shot
- Gate pulse 时重启
Mode 2: rate generator
- 计数为 1 时 OUT = 0，回到最开始
- duty cycle = N-1/N
Mode 3: square wave generator
- 计数小于 1/2 N 时，OUT = 0
Mode 4: software-triggered strobe
- 计数归零时 OUT 下降一个周期
Mode 5: hardware-triggered strobe
- 与 mode 4 相同，Gate pulse 时重启

信号

\(\overline{CS}\) - Chip select enable
\(A_0, A_1\) - address inputs select one of four internal registers

Programming the 8254

Each counter is programmed by writing a control word
Two write operation conventions
- 控制字先于计数值写入
- The initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte).